The present invention relates to an analog-to-digital converter operating in parallel and comprising a plurality of comparators in which each first comparator input is connected to an impedance network for supplying each of the comparators with its own predetermined reference voltage, and each second comparator input is connected to the analog signal input of the converter, the outputs of the comparators being connected to a corresponding number of digital signal outputs.
Such an analog-to-digital converter is described, for example, by J. Lambrechts in the article entitled "Optimale parallel-conversie door track/hold's", published in Electronica 85/7 (1985), pp. 23-27. In this prior-art converter the digital signal outputs are connected to an m-to-n converter which converts the digital signals at the m signal outputs to a digital word of n-bits, where m=2.sup.n. In this article the fact is pointed out that variation of sample delays constitutes a potential source of dynamic conversion errors in such analog-to-digital converters operating in parallel. The separate comparators have each a certain delay determined by the internal asymmetry in the two comparator branches, the lay out of the chip in which the comparator is structured and the sample rate at which the analog input signal is sampled. The delay is generally different for each of the comparators. The resultant sample delay differences between the adjacent comparators generally do not form a serious problem to low-frequency analog signals. However, if the frequency of the analog input signal increases, the differences between the various sample delays may result in missed codes and an extremely high differential non-linearity. The consequent errors depend on the length of the rise time and on the direction of the edge of the analog input signal.
Variations of the slope of a signal applied to the analog input sections of the comparators will lead, more specifically, to second or third-order distortions of the input signal as a result of the bandwidth limitation that holds for each of these analog sections.
It is an object of the invention to indicate in what manner the disadvantages resulting from the variation in sample delays can be reduced or eliminated with relatively simple means.